1. Field of the invention
This invention relates to an apparatus and method for the fabrication of semiconductor circuits. More particularly, it relates to an apparatus and method for the fabrication of semiconductor circuits, such as MOS semiconductor circuits, which are fabricated by forming semiconductor elements on a semiconductor wafer, and then wiring and connecting the elements to each other.
2. Description of the Prior Art
The technique of wiring semiconductor elements selectively with metal wirings has been called the master slice approach. One example of this technique is disclosed in the Japanese Patent Publication No 1-13223 "Semiconductor Integrated circuits".
The master slice approach has been developed to shorten the period from design to fabrication. This approach, therefore, did not have as its aim to improve the fabrication yield so, of cource, it did not show any effect for this aim.
Japanese Patent Publication No. 1-16013 "A method to determine the routes of wiring patterns" is known as one of the prior arts for improving the fabrication yield by a design phase approach. Following is a summary of this patent. In an LSI having a large scale of logics, the number of wiring patterns is enormous. As a result, the fraction defect by short-circuiting among the patterns increases to cause deterioration of the fabrication yield. In this patent, to prevent the deterioration in the fabrication yield, wiring regions should be divided using straight lines so as to break up patterns dispersed uniformly. The fraction defect by short-circuiting can, then, be reduced. When this technique is applied to LSIs having undergone highly developed fine processes, however, this technique does not prevent the deterioration in the fabrication yield caused by the changes in element characteristics increases as a result of the fabrication variation among elements' shapes or dimensions.
In LSIs having undergone highly developed fine processes, the basic data on how much the change in element characteristics increases or how big the fabrication yield has deteriorated depending on the fabrication variation among elements' shapes, are disclosed in the technical paper by B. Davari, et al., "High Performance 0.25 .mu.m CMOS Technology", IEDM Technical Digest, pp. 56-59, 1988. Especially in FIG. 5 of this paper, the dependent relation between the saturation transconductance and the effective channel length of sample devices is shown according to measured data. From this figure, it can be seen that the saturation transconductance is about 30 mS/mm for a p-channel FET having a 2.0 .mu.m effective channel length, 50 mS/mm for a p-channel FET having a 1.0 .mu.m effective channel length, 85 mS/mm for a p-channel FET having a 0.5 .mu.m effective channel length, 120 mS/mm for a p-channel FET having a 0.3 .mu.m effective channel length, and 200 mS/mm for a p-channel FET having a 0.1 .mu.m effective channel length.
According to the basic data, the device techniques of 2.0 .mu.m and 0.3 .mu.m are compared below.
In general, the effective channel length depends on the poly-silicon length in a gate area of an element. This poly-silicon length in a gate area, however, contains some degree of fabrication variation arising from the fabrication precision control in, e.g., the etching process included in the element fabrication processes. Even though much progress has been made in fine fabrication techniques, the fabrication variation mentioned above still exists to some degree. In the equipment of mass production, the variation is usually about .+-.0.2 .mu.m. As a result, in the device technique of 2.0 .mu.m, the saturation transconductance disperses from 25 to 35 mS/mm depending on elements. On the other hand, in the device technique of 0.3 .mu.m, the transconductance of elements shows a large variation such as from 85 to 200 mS/mm because the difference among channel lengths is from 0.5 to 1.0 .mu.m in this case. This fact means that the operation speeds of LSIs have a large variation such as more than double the transconductance variation, because the operation speed of an element is proportional to its transconductance. Thus, operation speeds of LSIs cannot be greatly improved even if fine device techniques are highly developed.
The following three problems arise as a result of the variation among operation characteristics, which are caused by the variation among element characteristics, such as operation speed.
First, deterioration of the fabrication yield occurs. The so-called output buffer of an LSI can drive a large outside electrical load, however, this becomes disadvantageous due to the variation among poly-silicon lengths in the gate areas of the elements. In other words, when the element is designed by assuming the maximum and the minimum limits of the variation in the poly-silicon length, the variation range becomes too wide to execute an optimum design. Even if the element is designed by taking into account of the minimum value, it may not be fabricated with the minimum value. That means it may be fabricated with the maximum value. In this case, a proper operation speed of the element cannot be obtained to cause the decline of fabrication yield. On the contrary, in the case where the element is fabricated having the minimum value against the designed value, that is, the maximum value, the drive current of the element becomes too large, and as a result, it causes distortions, such as ringing, in the waveform. This fact results in the waveform of an element departing from the required characteristic, thus causing the decline of the fabrication yield in LSIs.
Second, a difficulty in design for an LSI arises due to the fact that the operation speed of an element cannot be greatly improved. In LSIs, there are some functional modules, in which high operation speeds are required, such as an ALU and an incremental circuit. These modules sometimes determine the operation speed of the whole LSI. In prior arts, such circuits are designed, in general, by assuming the maximum variation value in the poly-silicon channel lengths of gate areas in elements. Although there has been progress in the fine process, element characteristics near the the maximum value haven't been greatly improved, and the required operation speed cannot be obtained easily. Thus, in designing element values, it is too difficalt to arrange the elements and circuits within an effective silicon area. This means that the optimum design for an LSI is difficult to accomplish.
Third, in LSIs made by the master slice approach, the problem of fabrication yield deterioration arises. With the progress made in the fine processes, as mentioned above, the difference between minimum and maximum limits in the gate length variation in elements, of which a cell is composed, becomes so large that the limit speed in operation is greatly varied for each product and lowers the yields of products.